1. Field of the Invention
The present invention relates to a semiconductor device and a method for making pattern data.
2. Description of Related Art
An interlayer dielectric layer provided in a semiconductor device has roles in insulating an upper wiring layer from a lower wiring layer, for example. If the interlayer dielectric layer does not have a flat surface, problems arise in that wiring layers formed on the interlayer dielectric layer may be cut.
Interlayer dielectric layers having an excellent planarization characteristic includes, for example, a silicon oxide film that is formed by reacting a silicon compound such as silane with hydrogen peroxide through a CVD method. For example, this technology is described in Japanese Laid-open Patent Application HEI 9-102492.
Although such a silicon oxide film is used as an interlayer dielectric layer, a global height difference is created along a border between a region in which large patterns of wiring layers are formed and a region in which small patterns of wiring layers are formed. More specifically, a main surface of a semiconductor substrate includes a region where relatively large patterns of wiring layers are formed and a region where smaller patterns of wiring layers are formed. The silicon oxide film has a high level of flowability. Accordingly, the silicon oxide film formed over the region where the small patterned wiring layers are formed typically has a thickness smaller than the thickness of the silicon oxide film formed over the region where the large patterned wiring layers are formed. Due to the thickness difference, a global height difference is created.
As the number of wiring layers increases, the number of interlayer dielectric layers increases. A difference in thickness occurs in each interlayer dielectric layer, and the thickness differences are added up. Accordingly, as the number of interlayer dielectric layers increases, the global height difference becomes greater.
Problems caused by greater global height differences are discussed below. When a through hole is formed in an interlayer dielectric layer, a resist is used. A focus margin in exposing the resist becomes smaller when the global height difference becomes larger. As a result, the resolution at the resist lowers. As a consequence, a designed shape of a through hole may not be formed or a through hole may not be formed at all.